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This invention relates to electrical devices and, more particularly, to high voltage electrical devices including monocrystalline semiconductor substrate layers and epitaxial base layers utilizing positive bevel angles to increase operational voltage.
The use and complexity of electronic equipment continue to increase around the world, and the functions performed by electronic equipment continue to improve and expand. As complexity increases and functions expand and improve, the operational requirements of the electrical devices used in electronic equipment have also increased. The newly introduced high definition televisions, for example, require diodes rated at 1700V, but currently available diodes are only rated at 1600V. This has required high definition television manufacturers to test for and choose the best of the available 1600V diodes leading to increased cost.
To construct a high voltage diode requires a high resistivity layer having a sufficient thickness and resistance to provide a reverse voltage blocking capability. Further, it is necessary to control and minimize the electric field at the edges of the diode. In a typical construction, the low resistivity epitaxial layer is deposited on a highly doped, single crystal semiconductor substrate layer. To maintain the purity and single crystal structure in the epitaxial layer, the epitaxial layer must be deposited at a low rate of about one (1) micron per minute. However, as the thickness of the epitaxial layer increases, it becomes more difficult to maintain the single crystal structure with a low defect level. Thus, there is an increased number of defects in the epitaxial layer, which can undesirably limit the operational parameters of the diode. Further, the deposition rate of the epitaxial layer must be slowed further thereby increasing manufacturing cost and allowing the junction between the doped substrate and the pure epitaxial layer to become more gradual due to diffusion from the substrate to the epitaxial layer.
Attempts to address these problems have lead to the development of entirely diffused structures. However, such diffused structures offer less attractive electrical parameters. For example, because the P/N junction of a diffused structure is gradual, the voltage drop or loss across a high voltage, fast switching, diffused structure diode can be as high as 5V. In contrast, the voltage drop for a high voltage, fast switching, epitaxial structure diode with an abrupt junction can be as low as 1.7V. Further, it is commercially unfeasible to manufacture more than one diffused structure diode on each wafer because of the high diffusion depth necessary to provide sufficient thickness in the bottom layer to keep the wafer from breaking after moats are etched to form the separate diodes. Additionally, diffusion beyond normal depths can warp the wafers making them more difficult to handle and increases the occurrences of breakage.
There is, therefore, provided in the practice of the invention a novel electrical device, which is inexpensive and easy to manufacture, for use in high voltage applications. The electrical device broadly includes a high resistivity substrate layer, a low resistivity base layer, and a low resistivity top layer. The substrate layer is formed by crystalline growth method to form an ingot which is sliced to at least a desired thickness of the substrate layer, and the base layer is an epitaxial layer deposited on a surface of the substrate layer.
In a preferred embodiment, the top layer comprises a diffusion layer, and the substrate layer is an Nxe2x88x92 conductive type with a thickness in the range of approximately 50 to 130 microns. This thickness provides a device rated at between approximately 1500V and 2200V, respectively. The size of the device can be changed to accommodate various forward current and forward voltage combinations. A typical 6.5 amp device has top dimensions of approximately 2500 microns by 2500 microns. The top layer is N+ type and has a central recess minimizing, in a central portion of the electrical device, the distance between the top layer and the epitaxial layer, thus minimizing the electric field at the edge of the device. The base layer is preferably a P+-type layer and has a thickness in the range of 200 to 400 microns to provide sufficient thickness needed to maintain the mechanical structure and the electrical base after channels are etched throughout the remaining process steps such as passivation of the high voltage junction, metallization, and any photolithography steps employed in the process as needed.
It is further contemplated in the practice of the invention that the device is separated from a semiconductor wafer along with a plurality of other devices. The wafer includes a high resistivity substrate layer formed with a crystalline growth method, a low resistivity base layer, and a low resistivity top layer. The wafer also includes a plurality of intersecting channels forming a grid in the wafer to separate the individual electrical devices.
In a preferred embodiment, the base layer is an epitaxial base layer doped with germanium to control the stress in the wafer. The wafer is generally circular, and when the diameter of the wafer is approximately 100 mm and has 2500 micron by 2500 micron devices formed thereon, the wafer includes approximately 1000 individual devices.
It is still further contemplated in the practice of the invention that the electrical device is formed with a method for fabricating a plurality of high voltage devices. In the method, a high resistivity ingot is grown with a monocrystalline structure by a crystalline growth method, and at least one wafer is sliced from the ingot to form a substrate. A highly doped, low resistivity base layer is formed on a first surface of the substrate, and a low resistivity top layer is formed on a second surface of the substrate. The wafer is then divided to form the separate devices.
In a preferred embodiment, the process is repeated with additional wafers sliced from the ingot and with still more wafers sliced from additional ingots. Forming the base layer preferably comprises depositing the base layer on the substrate. The method also includes doping the base layer with the dopant providing opposite polarity to the substrate and a stress control dopant, preferably germanium, and adjusting the concentration of the stress control dopant, so that the wafer is substantially flat and has minimal stress. The low resistivity top layer is preferably formed by diffusion
Accordingly, it is an object of the present invention to provide an improved electrical device for high voltage applications.
It is another object of the present invention to provide an improved method of fabricating high voltage electrical devices.